1.Field of the Invention
The present invention relates to a method of manufacturing an electronic device having fine patterns, more particularly to a method of manufacturing a semiconductor integrated circuit device having a plurality of fine circuit patterns.
2. Prior Art
In the manufacture of semiconductor integrated circuit devices, repetitive use is made of an epitaxial process such as a chemical vapor deposition (CVD) process, a doping process such as ion implantation, a lithographic process, and an etching process. The operation speed and integration density of semiconductor integrated circuit devices can be effectively improved by miniaturizing the circuit patterns and enhancing the dimensional accuracy, as has increasingly been done in recent years. The miniaturization of circuit patterns mainly depends on lithography, so lithography plays a vital role in the manufacture of semiconductor integrated circuit devices.
Lithographic technology mainly employs a projection aligner that forms device patterns by transferring the pattern of a photomask mounted in the projection aligner to the surface of a semiconductor wafer. At this time, the exposure area of a high-resolution projection aligner is smaller than the area of a semiconductor wafer, so the exposure is divided into a plurality of shots which are stepped or scanned to repeat the exposure of the chip area a plurality of times. The size of a chip depends on the product to be made, so a photomask is, in general, provided with an outer frame referred to as a shade area made of a metal such as chromium (Cr) so that a desired shot size can be obtained. In this way, the single chip areas exposed by the plurality of shots are prevented from overlapping, and a scribe area is provided around the edge of each chip for dicing.
The need for higher integration and faster device operation has led to the increasing miniaturization of the patterns formed by lithography in recent years. In this context, research and development aimed at shortening the wavelength of exposure light used for exposing patterns in an optical aligner are being pursued.
Furthermore, a halftone phase-shifting exposure method is now being used. A halftone phase-shift mask is a translucent film (referred to as a halftone film) formed on a transparent plate to dim the exposure light and shift its phase. In general, a transmittance in the range of 1% to 25% of the exposure light is considered desirable.
Exposure light which passes through a halftone film is phase shifted with respect to exposure light which does not pass thorough the film. Either a single layer or a multi-layer halftone film can be used to produce the phase difference. Although phase differences of 180xc2x0 and odd multiples thereof are needed to obtain the highest resolution, other phase differences within a range of 180xc2x0xc2x190xc2x0 are also effective in improving resolution. It is known that use of a halftone mask can improve the resolution by about 5% to 20%.
Descriptions of halftone phase-shifting can be found, for example, in documents such as JP-A No. H5-181257.
As described above, a halftone phase-shifting method is known as an exposure method that can resolve fine-dimensioned patterns with high resolution. This exposure method, however, has many problems as described below, making it difficult to obtain sufficient pattern transferring accuracy.
The halftone phase-shifting method causes interference between exposure light which has passed through the halftone part and exposure light which has passed through apertures therein, in the vicinity of the boundaries of the apertures and the halftone part, to enhance the optical contrast, thereby improving the resolution and exposure tolerances. For this reason, it is very critical to control the amount of exposure light passing through the halftone part, or the transmittance of the halftone part, and the amount of the phase shift.
In addition, the dimensional accuracy of the halftone film pattern has a profound effect on the dimensional accuracy of the transferred pattern. For a fine pattern near the resolution limit of the projection lens, the optical contrast becomes substantially lower due to light diffraction which, together with a factor referred to as the mask error enhancement factor (MEF), makes the dimensional accuracy of the transferred pattern lower than that of the pattern on the mask. The MEF is an indicator showing the amplification of the dimensional difference xcex94Lm of a transferred pattern in relation to the dimensional difference xcex94Lw of the pattern on a mask, and is given by the equation MEF=xcex94Lm/ (Mxc2x7xcex94Lw), where M is the reduction factor of the projection lens. If a 5xc3x97 lens is used, then M is ⅕. In a case with a fine pattern using a halftone phase-shift mask, the pattern is generally transferred with an MEF of 2 to 3, so that unwanted variations in the dimensions of the pattern on the mask are amplified by a factor of 2M to 3M.
In the manufacturing processes of a semiconductor integrated circuit device, a step that requires particularly high dimensional accuracy in a fine pattern is the patterning step for the gate electrodes of transistors. As the dimensions of the gate electrodes become smaller, the operation speed of the transistors becomes higher. High dimensional accuracy of the gate electrodes enables stable operation of the circuit and thus enables high-speed circuits to work together, consequently increasing the added value of a semiconductor integrated circuit device. In addition, if fine patterns can be formed with higher accuracy in the wiring patterning process, interconnection wirings can result in a higher packing density and shorter length, which also contribute to high-speed circuit operation and a higher integration density.
However, if the conventional halftone phase-shift exposure method is adopted for extremely fine gate, wiring, and hole patterning processes, there is a problem in that sufficient dimensional accuracy cannot be obtained due to the inadequate controllability of the phase and transmittance of the halftone phase-shift mask and variations of dimensions on the mask, and consequently the reproducibility and yield of the manufacturing process cannot be improved.
It is an object of this invention to provide an improved method of manufacturing an electronic device having fine dimensional patterns.
It is another object of this invention to provide an improved method of manufacturing a semiconductor circuit device having fine circuit patterns, so that higher integration levels and higher-speed operation can be obtained.
It is a further specific object of this invention to provide an improved method of manufacturing a high-speed, highly integrated semiconductor integrated circuit device by forming fine patterns for gate electrodes, wirings, and holes with better dimensional accuracy.
Typical aspects of the invention disclosed herein will be described below. Although the following description focuses on a method of manufacturing a semiconductor integrated circuit device, the invention is also applicable to methods of manufacturing other electronic devices having extremely fine patterns, such as liquid crystal display devices, micro machines, and superconductive devices. In accordance with a first aspect of the invention, a mask having shade areas made of resist external to the halftone phase-shift pattern is used to expose a photosensitive film provided on the surface of a workpiece such as a semiconductor wafer with an oblique illumination system to transfer a fine pattern.
The mask or other workpiece is exposed by stepping or scanning the exposure shots, thus repeating the exposure a plurality of times, in such a way that the resist shade areas are transferred in a partially overlapping manner. This makes it possible to transfer fine patterns with high accuracy to a plurality of adjacent areas on a photosensitive film provided on the main surface of the workpiece and thereby form electronic devices such as semiconductor integrated circuit devices.
The resist shade area of the first aspect of the invention is formed outside the areas in which circuit patterns having halftone characteristics are disposed, whereby overlapping exposure of those areas during the plurality of exposure shots can effectively be prevented.
In addition, although the halftone phase-shift pattern may be constructed by providing projections and depressions on a transparent plate surface, in order to form a finer pattern with higher accuracy and better reproducibility, it is more desirable to deposit a halftone film on the surface of the transparent plate and pattern the film. A halftone phase-shift pattern constructed with a halftone film can offer improved mutual alignment accuracy of the halftone phase-shift mask and work piece, or wafer, if alignment marks are provided for reference on the halftone film.
In accordance with a second aspect of the invention, an electronic device such as a semiconductor integrated circuit device is fabricated as follows: in forming fine holes with dimensions that are not expanded too much two-dimensionally (that is, in the x and y directions) in a dielectric film on the main surface of the wafer to attach electrode terminals extending to the semiconductor area in the wafer, or to form interconnections between wiring layers, a first fine pattern transferring process is performed, which transfers a fine hole pattern to a plurality of adjacent areas on a first photosensitive film provided on the main surface of the wafer by repeatedly stepping or scanning an exposure using a first halftone phase-shift mask with a shade area made of chromium or another metal surrounding a halftone phase-shift pattern corresponding to the fine hole pattern, or a so-called binary mask with a pattern corresponding to the fine hole pattern that is formed by a shade film; in forming narrow or rectangular fine patterns disposed in close proximity to each other, such as gate electrode patterns and wiring patterns, (that is, a plurality of patterns at least having larger longitudinal dimensions than the hole pattern mentioned above, in other words, a plurality of patterns that extend farther in the x or y direction than the hole pattern mentioned above), a second fine pattern transferring process is performed, which transfers a fine wiring pattern to a plurality of adjacent areas on a second photosensitive film provided on the main surface of the wafer by repeating oblique illumination exposure shots a plurality of times with a stepper or a scanner using a second halftone phase-shift mask with a shade area made of resist external to the halftone phase-shift pattern formation area corresponding to the fine pattern.
Furthermore, in the second aspect of the invention, the alignment accuracy of the first mask for forming the fine hole pattern and the second mask for forming the slim electrode and the wiring pattern with respect to the workpiece such as a wafer can be improved by forming the alignment marks of the first mask in the chromium or other metal shade film and the alignment marks of the second mask in the halftone film surrounded by the resist shade area. That is, a fine circuit pattern can be formed with higher dimensional accuracy and higher alignment accuracy thorough lithography by using either a halftone phase-shift mask with a shade area made of resist or a metal shade area mask with alignment wafer marks formed by metal, or both, according to the type of fine patterns to be formed; that is, gate electrodes, wiring, or holes.
Furthermore, in accordance with a third aspect of the invention, the mask used in the first aspect of the invention described above can be made to have no resist material in the fine pattern formation area, so it is possible to form a resist band-like shade area with resist material that fluoresces in response to incident light and easily inspect resist residue defects in the fine pattern part by irradiating the area with inspection light, thereby improving production yields of electronic devices.
In addition, in accordance with another aspect of the invention, it is possible to effectively prevent contamination of fine pattern masks and electronic devices by performing exposure processing by using a mask with a resist shade film formed outside the fine pattern formation area and using the outer region of a mask plate having no resist film to be mounted on the supporter of an aligner and transportation means for transporting the mask, thereby keeping the resist material from coming in contact therewith.
When adopted in the fine patterning processes for gate electrodes, holes, and wiring, the various manufacturing methods of the present invention described above can improve reproducibility and yields in the manufacture of electronic devices such as high-density semiconductor integrated circuit devices.
In order to make the manufacturing process of photomasks easier and more accurate, for example, JP-A No. H5-289307 has disclosed a method of forming a mask pattern with a resist film. This mask is a so-called binary mask comprising exposure light transmitting parts and shade parts with sufficiently low transmittance, which inherently has no problem of overlapping exposure shots.
An example of the use of resist shade areas in a halftone phase-shift mask is found in JP-A No. H9-211837, which prevents sub-peak transfer when circuit patterns are formed, and forms a so-called rim-type halftone mask in which only areas close to the pattern edge are half-toned.
This invention differs in its objects and effects from these methods and also differs in the locations at which resist films are formed.
This invention enables fine patterns to be formed with higher dimensional accuracy and alignment accuracy, making it possible to manufacture electronic devices, such as higher-speed and highly integrated semiconductor integrated circuit devices, with better reproducibility.